1. Technical Field of the Invention
This invention pertains to an I/O bus to host bridge in a processor system. PCI/host bridge apparatus and method in which at least one bridge shares a common TCE cache between DMA reads and writes.
2. Background Art
A PCI host bridge provides an interconnect between an I/O subsystem and one or more processors in a processing system. (See, xe2x80x9cPCI Local Bus Specificationxe2x80x9d Revision 2.2, Dated Dec. 18, 1998.) A host bridge typically provides data buffering capabilities for transferring read and write data between the I/O subsystem and the processors. Read and write commands or transactions that originate on the PCI bus and are destined for system memory are typically referred to as DMAs.
A PCI host bridge may also provide a means of translating addresses from a PCI memory address space to a system memory address space. A host bridge chip may provide a hardware mechanism to fetch table entries from system memory which describe how to map PCI addresses into system memory addresses. The host bridge uses a table entry to determine the system memory location to which a DMA operation will be directed.
Previous host bridges have combined the function of the DMA read data buffering and translation table lookup into a read xe2x80x9cchannelxe2x80x9d. These channels are a partitioning of a finite data buffer resource. A DMA read operation is allocated to one of these channels which holds both the translation table entry and the associated data buffer. The read channel can act as a cache for DMA read data and the translation table entry, which means that the channel can be accessed multiple times by separate DMA read transactions. This read channel is subject to reallocation due to the finite buffering resources available. When reallocation occurs, both the buffered data and the associated translation table entry are lost.
DMA writes also require allocation of a data buffer and a translation table entry repository. DMA write data are not cached but are merely buffered to provide the capability of xe2x80x9cpostingxe2x80x9d the write and freeing the PCI bus earlier than otherwise possible if buffering were not provided. The translation table entries for DMA writes, however, are kept in a cache. This cache is separate from the translation table entries that are kept for the DMA read channels.
U.S. Pat. No. 6,003,106 by Guthrie et al relates to checking cached DMA read data against new DMA read data in a coherency mechanism designed to avoid the use of stale read data. Guthrie does not allow multiple usage of translation control elements by multiple DMA read channels, nor allow sharing of a TCE caching mechanism between multiple I/O buses.
It is an object of the invention to provide an improved PCI host bridge apparatus and method.
It is a further object of the invention to provide a PCI host bridge apparatus and method which more efficiently utilizes limited resources available for caching translation control entries (TCEs).
It is a further object of the invention to provide a PCI host bridge apparatus and method in which cached TCEs are allocated to DMA reads or writes based on dynamic usage rather than fixed at design implementation.
It is a further object of the invention to provide a PCI host bridge apparatus and method in which reallocation of a read channel does not necessarily result in the loss of a TCE.
It is a further object of the invention to provide a PCI host bridge apparatus and method in which repeated reads or continued reads do not necessarily suffer the latency of re-fetching a TCE when a channel reallocation occurs between read attempts.
It is a further object of the invention to provide a PCI host bridge apparatus and method through which an increased maximum sustained data rate may be achieved.
It is a further object of the invention to provide a PCI host bridge apparatus and method wherein DMA reads and writes that use the same TCE require only a single TCE fetch.
In accordance with the invention, a system and method is provided for sharing I/O address translation elements across multiple I/O bus bridges. A TCE manager is provided for retaining in cache a TCE entry associated with a discarded channel or associated with a previously completed write for association with a new channel responsive to a subsequent read request for a memory page referenced by the TCE entry or for use by a subsequent write operation to a memory page referenced by the TCE entry.